CPU 6502 Module

Episode 1

Let's start this series with a description of the MOS 6502 CPU, learning what is the function of every pin (the pin out) and how its internal architecture works.

We will study its internal registers, what are they used for and how to create this PCB Board from scratch. We will finihs with and expetiment that will allow us to learn the RESET sequency and execute our first 6502 instruction.

CPU 6502 Overview

A CPU is the central processing unit where everything that happens inside a computer is originated, here the mathematical calculations and addressing of the computer are typically performed.

The 6502 CPU was created by Chuck Peddle and Bill Mensh of MOS Technologies and was widely used in the late 70s and early 80s. This family of CPUs was used in the Apple 1, the Apple 2 in its 6502 packaging, in the Commodore 64 in its 6510 variant and in the Atari VCS in its 6507 variant.

The 6502 is still widely used today, having current versions from the manufacturers USM and WDC, the current version being the 65C02 which adds some extra assembly instructions and greatly reduces electrical consumption.

Pinout CPU 6502

This chip has a DIP 40 format (dual in-line package) with the following functions on its pins or legs.

VPB (OUTPUT) The B means Bar, for this pin to be activated the voltage has to be a digital Low or 0v. This pin is used to indicate that an address is being accessed via a vector during an interrupt. It is only used in the WDC version of the 6502 chip, in any other manufacturer’s chip it is just an additional GROUND. With the WDC brand it can be left disconnected with the other brands it must be connected to ground.

RDY (INPUT) The ready pin is used to tell the microprocessor that it has to stop and maintain the current state, refreshing all registers and without losing any data. To activate it and stop the pin, it waits for a low state or 0 Volts. For example, upon receiving a Low state (0 volts) on the pin, all the output lines will maintain the current values they had, showing which direction they were looking for. It is ideal for doing an instruction-by-instruction study of the chip.

PHI1 o ɸ1 (OUTPUT) Clock Output Pin, this is a clock output to connect to other devices. PHI1 is typically the PHI2 signal but inverted.

IRQB (INPUT) Interrupt pin. By connecting this pin to 0V, if interrupts are enabled, the processor will save the contents of the current registers and search the vector memory locations FFFE and FFFF and read the contents to find a second memory location that contains the first instruction to execute to service this interruption.

MLB (OUTPUT) The Memory lock pin is used to maintain the integrity of Read-Modify-Write instructions in a multiprocessor system. When it presents a Low value or 0 volts, it indicates that some other circuit must arbitrate the bus cycle. It is an Output pin

NMIB (INPUT) Non-maskable interrupt pin. By connecting this pin to 0V the processor will save the contents of the current registers and search the vector memory locations FFFA and FFFB for another memory location that contains the first instruction to execute to service this interrupt. This type of interruption is unconditional and will always be honored.

SYNC (OUTPUT) Sync Pin. The Processor instructions cycle starts by reading the opcode of an instruction, this is indicated with the SYNC pin being set to high. When the processor looks for an opcode the pin goes high and remains high for the first clock cycle of the instruction cycle, the fetch phase. We are going to study it when designing a program that interprets when an instruction is represented on the data bus.

VDD o VCC (INPUT) Energy Pin. The processor typically works with +5v.

AB0 a AB15 (OUTPUT) Addressing Bus Pins. They are unidirectional pins on which the processor will write the addresses of the devices tha it addresses (memories, other chips on the board, I/O registers, etc.). Being a 16-bit bus, it addresses up to 65536 bytes or from $0000 to $FFFF.

VSS (INPUT) Ground pin, this pin connects to the common ground of the design.

DB0 a DB7 (INPUT/OUTPUT) Data Bus Pins, This is a bidirectional bus that allows data to be received and written (along with the R/W bit) to memories and I/O registers.

R/W (OUTPUT) Read/Write Pin. This pin indicates whether the processor is performing a read or a write. When it presents a 1 or +5v, the processor is performing a read; when it is at 0 or the Low state Ov, it is performing a write.

NC No Connect, this is a pin that should not be connected since it is not connected to anything inside the processor. Not used

BE (INPUT) Bus Enable pin, when this pin is High or +5v the address, data and RW pins are active, when it is low or 0v they remain with high impedance, removing the processor from the bus.

PHI2 ɸ2 (INPUT) Clock input pin, This pin allows connecting an external clock to the processor to synchronize with other devices. It is the pin that we are going to use in our experiments to connect an external clock.

SOB (INPUT) Pin by Set Overflow. When this pin receives a change from high to low, it turns on the Overflow bit in the Status Register of the processor (bit 6). It was not used much in the past and is not recommended for use now.

PHI2O ɸ2O (OUTPUT) Clock Output Pin, this is a clock output to connect to other devices with the same waveform as the clock received in PHI2.

RESB (INPUT) Reset pin, this pin is used to reset the processor when connected to 0v. The reset will take 7 clock cycles and will search the memory locations FFFC and FFFD where the vector (another memory location) that has the first instruction to be executed is located. The reset must be held at 0v for at least two clock cycles to be recognized.

General connection recommendations

It is recommended that the RDY IRQ NMI SOB BE pins be connected to +5v through a 1K resistor.

The VP pin must be connected to 0v through a 1K resistor, in non-Western Design Center models this pin is only a GROUND.

CPU 6502 Operation Description

Architecture

The 6502 is an 8-bit processor since all its machine code instructions (opcodes) can be referenced using 8 bits. The internal architecture is divided into two parts, one section with the registers and another with that performs the control operations, the signals that cause data transfers are in the control section.

In the diagram we can see that the reset signal RESB enters the Interrupt Logic and Instruction Decode box, this is why a reset is nothing more than a BRK instruction (binary code 0000 0000) or $00 loaded from the hardware.

Instruction set

The 6502 machine code has instructions that can operate without arguments, with a single explicit argument or with two arguments.

I added to the diagram some extra instructions from the 65C02 model (those marked with a dot in the following table) that I DO NOT recommend using in order to maintain compatibility with the entire 650X family such as the 6510 and the 6507, they save some steps by not having, for example, to go through the accumulator to save register X on the stack with the PHX instruction.

The 65C02 is a more modern version of the MOS 6502, with the advantage of being fully static so the clock can be stopped and the registers do not lose their values.

Clock Speed

The original 6502 processor supports a clock speed of up to 1Mhz, with modern versions supporting higher speeds.

Registers

The number of registers and the way to access them are the same for the entire family 0f 6500 processors, these are the familiar Acummulator, X and Y, the Status Register and the Stack Pointer, all of these registers are 8 bits longs but for the Program Counter which is 16 bits long in order to address up to 65536 memory locations.

Addressing modes

The 6502 has different addressing modes, being able to load data directly into memory, or a literal number to the accumulator, or data in indexed form and even apply functions that work with the accumulator going through memory.

Addressing and Data Bus

The processor has 16 address lines (pins A0 to A15) being able to handle between memory and I/O registers up to 64Kb (2ˆ16 = 65536 bytes) and 8 data lines (pins D0 to D7) to be able to move information of up to 1 byte per clock cycle.

The 20c CPU 6502 Board Circuit

The following graphic shows the circuit that explains the operation of the CPU 6502 board.

The circuit has the following elements:

SOCKET CPU 6502

Which is physically represented as a 40-pin DIP-40 socket, to each of these pins a Netlist was connected representing each of the functions of the pins, for example, netlist A0 represents pin A0 that will be connected to all the elements that have to be connected to the line or trace of address 0.

It has connected the netlists from A0 to A15, D0 to D7 and all the EXPANSION BUS netlists.

HEADER ADDRESS

This is a 16-pin female header which is used to connect the address bus, it has 16 netlists connected (or connections between several pins that have the same information). These netlists correspond to pins A0 through A15.

We have two of these connectors to be able to have the information at the top and bottom of the board and make interconnections with other boards.

HEADER DATA

This is an 8-pin female header which is used to connect the data bus, it has 8 netlists connected (or connections between several pins that have the same information). These netlists correspond to pins D0 through D7.

We have two of these connectors to be able to have the information at the top and bottom of the board and make interconnections with other boards.

HEADER EXPANSION

This is a 16-pin female header which is used to connect the address bus, it has 16 netlists connected (or connections between several pins that have the same information).

These netlists correspond to some netlists connected directly to the pins of the 6502 CPU, such as:

RST, CLOCK, RW, PHI2_OUT, RDY, IRQ, NMI, PHI1_OUT, ML, SYNC, SO, BE, VP

And others that allow us to pass information from other boards if we wanted to, using the same expansion boards with other signals of our choice:

E13, E14 and E15

We have two of these connectors to be able to have the information at the top and bottom of the board and make interconnections with other boards.

HEADER POWER y GROUND

This header has two pins and they are connected to the 5V and GROUND layers respectively. We have four of these connectors, one in each corner of the board.

We also have 5V and GROUND headers with 8 pins each to be able to connect different pins of the 6502 that need to be at digital values of 0 or 1 and cannot be floating. They are connected to the 5V and GROUND layers respectively. We have two of these 5v connectors and two GROUND connectors giving us a total of 16 pins for each value. It is always recommended to connect it to the corresponding pins of the CPU with resistors of at least 1K ohm.

RESET CIRCUIT

It consists of a resistor connected to +5v and to the reset button that maintains it at the digital value 1. When the reset button is pressed, being connected to the reset pin of the 6502 and GROUND 0v, it passes the digital value 0 to the cpu and it begins the reset cycle.

CAPACITOR

We have a 0.1 microFarad capacitor so that when the CPU starts up it can have the extra peak energy it needs

HOLES for SCREWS

To be able to fix our PCB Board to different places, it has 6 holes for 3mm or M3 screws.

NETLIST

The components are connected to each other through an object called netlist which allows us to have cleaner diagrams.

This works in such a way that everything that has the same name belongs to the same netlist and must be connected together when we make the PCB traces. For example, in the diagram we can see pin 33 of the CPU socket with a netlist called D0, it must be connected to pin 1 of the header data, which is also connected to netlist D0.

The 20c CPU 6502 PCB Board

The following PCB explains how the elements and traces are located to connect our circuit. The PCB is 4 layers, having in the layer called TOP all the connections of our netlist through traces, which are thin layers of copper that connect them as if they were cables.

We have two special layers called 5v and GROUND where we will connect the power and ground connections. By using these connections on separate layers we save many centimeters of traces that should be connected to pins with the 5V and GROUND voltages and we can directly connect these pins to the corresponding layer.

Another advantage of having an entire layer for GROUND is being able to isolate electrical noise from the connections between components.

Finally we have the BOTTOM layer where our components are soldered and we have additional connections.

3D modeling

When we finish making our Board we must proceed to 3D modeling it to see how it looks and if we like the placement of the components.

Source file generation

In order to send our PCB to be manufactured we must have at least 3 files:

1..gerber file where we tell the manufacturer how to assemble our board

2. BOM or Bill of materials file where all the components that make up our board are located with the manufacturer's product code.

3. Pick and Place file where we tell the manufacturer how to place the components on our PCB board.

You will find these files previously generated in the Osolabs github.

https://github.com/osolabstech/The20c/tree/main/Episode1_CPU6502

We also included files to be able to edit the circuit with EasyEDA or Altium Designer software.

Gerber_v03_CPU6502_4Plane.zip

This file contains all the data to generate our PCB board.

BOM_v03_CPU6502_4Plane.xlsx

It contains all the components of our board and the manufacturer's code that identifies that component.

PickAndPlace_v03_CPU6502_4Plane.xlsx

It indicates where on the PCB each component goes and what layer it should be located on.

ProDoc_v03_CPU6502_4Plane.epro

File for EasyEDAPro with the circuit and the PCB which can be edited.

Altium_Circuit_v03_CPU6502_4Plane.schdoc

Contains the circuit design editable with the Altium Designer program.

Altium_PCB_v03_CPU6502_4Plane.pcbdoc

Contains the PCB design editable with the Altium Designer program.

cpu6502_3dModel.png

It is an image of the PCB model in 3 dimensions

cpu6502_Circuit.png

It is an image of the circuit of the CPU 6502 board

PCB_v03_CPU6502_4Plane_2024-06-29.pdf

It is a PDF with a drawing of each layer of the PCB

Preparation of the CPU Board

Upon receiving our board from the factory and before starting as soon as we take it out of the box, there are some tasks that we must do to be able to make the most of it

1. Remove handling edges from the board

2. Clean the board with isopropylic alcohol.

3. OPTIONAL - Put a 40-pin ZIF socket in the 6502 socket.

4. Put the 6502 cpu in the socket

1. Adjust the chip legs to fit in the socket
2. Align pin 1 of the 6502 chip with pin 1 on the socket
3. First insert one side of the chip, placing it diagonally and then the other side
4. Check that no legs were bent
5. Press and verify that all legs are well adjusted in the socket

5. Put screws to support the board so that it is raised above the surface.

Connection Guide for The 20c 6502 CPU board

We are going to explain how to connect the different components of the board to get it for our experiments. This is a configuration with all the boards that we are going to use even if we have not seen them yet. You can keep this section as a reference when you assemble the entire 20c.

CPU 6502

To configure the 6502 CPU board we are going to make the following connections.

Connect all the ADDRESS BUS pins from A0 to A15 to the external board to which we want to carry the signal. It can be directly to the ROM or RAM board, a BUS ADDRESS DATA EXPANSION board or any other board to which we want to carry that signal from the processor. Let's remember that the address bus addresses are generated in the processor.

We connect all the DATA BUS pins from D0 to D15 to the external board to which we want to carry the signal. It can be directly to the ROM or RAM board, a BUS ADDRESS DATA EXPANSION board or any other board to which we want to carry that signal from the processor.

Connect a cable from the CLOCK header board CLOCK 555 OUT pin CLK to the CLOCK pin of the EXPANSION BUS.

Connect a cable from the CPU board to the board to which we want to give a clock signal to the CLOCK pin of another EXPANSION BUS.

Connect the RDY pin of the EXPANSION BUS to 5v with a 1k ohm resistor.

Connect the IRQ pin of the EXPANSION BUS to 5v with a 1k ohm resistor.

Connect the NMI pin of the EXPANSION BUS to 5v with a 1k ohm resistor.

Connect the SO pin of the EXPANSION BUS to 5v with a 1k ohm resistor.

Connect the BE pin of the EXPANSION BUS to 5v with a 1k ohm resistor.

Connect the VP pin of the EXPANSION BUS to 0v with a 1k ohm resistor.

Connect the 5v and GROUND pins to a 5V and 0v source, respectively.

I suggest the following color guide if we are going to use cables with male/male dupont type terminals:

Experiment 1 - Viewing the Reset process and the NOP instruction

Let's see how the RESET of our CPU and the NOP operation work. For this experiment we are going to use an external CLOCK that we will study in detail in Episode 2 and a connection to an Arduino Mega through the Arduino connector which we will develop in Episode 3.

We are going to hardcode our 6502 CPU to execute the non-operation instruction NOP, it is coded as EA in the 6502 machine language instructions.

EA is translated into binary as 1110 1010 and this is what our processor will wait on its data pins to be able to read that instruction. In order to do this we are going to connect 8 resistors to our data pins as follows:

If we run a reset sequence by touching the RESET button on the CPU 6502 board and observe the result, we will see how it executes the reset in 7 clock cycles and goes to the memory positions FFFC and FFFD where the RESERT vector is (another memory position ) it has the addresses of the first instruction to execute. It takes 7 cycles since a RESET it is a BRK or BREAK instruction loaded by hardware through the RESET pin.

The reset must be held at 0v for at least two clock cycles to be recognized.

We can see that after execution it will read EA or the non-operating NOP instruction as the first instruction and will continue executing it since it is hardcoded with resistors in the data bus.

The Program Counter is incremented by 1 after the execution of each instruction, which is why we see that it goes from EAEA to EAEB, then EAEC, etc. Always getting as opcode EA.

It is repeated twice because each EA instruction takes two clock cycles to execute.

This concludes our first experiment where we saw how the CPU 6502 performs the RESET sequence and reads a first instruction.

Conclusions

The CPU 6502 Board will allow us to connect a CPU 6502 to carry out experiments very quickly since it easily opens the CPU pins on ADDRESS, DATA and EXPANSION bus and gives us a pre-installed reset button.

The CPU 6502 in operation

To visually see how to connect a 6502 CPU to the 20c, as always, I leave you with a detailed video of the series. In this we are going to see how the pins are connected, and how to perform our experiments. Find the video of Episode 1

https://www.youtube.com/playlist?list=PL1OpW6G6pEzMtTNEjPg9Uvo_5qGXiU20o